The present invention relates to a semiconductor memory device having a plurality of memory cells arranged in a two-dimensional (row and column) matrix array, and more particularly relates to a semiconductor memory device having a large-scale storage capacity and high-speed operation for reading information out of memory cells by decoding signals for row selection in two stages.
The miniaturization and high performance of electronic apparatus have been accompanied by increasingly large-scale storage capacity and high-speed operation of semiconductor memory devices mounted on electronic apparatus.
At present, some semiconductor memory devices which have more than one million memories within a one square centimeter chip, and in which the access time is less than 50 nano-seconds (5.times.10.sup.9 sec). Furthermore, technological advancement continues to demand large-scale capacities and higher speed operation of semiconductor memory devices.
In a conventional semiconductor memory shown in FIG. 1, a device is basically comprised of memory cell arrays 10 which are constructed by a plurality of memory cells 11 respectively arranged in a matrix and each storing one piece of data, a row selection decoder 20 for selecting a desired word line 12 which connects a plurality of memory cells arranged in rows, and a column selection decoder (not shown) for selecting a desired bit line (not shown) which connects memory cells arranged in columns.
Decoding operation in the conventional semiconductor memory device shown in FIG. 1 is performed as follows. A plurality of address signal lines 21 supplies the row selection decoder 20 with different row address signals for causing the decoder 20 to select a specified word line 12 corresponding to one of the address signals. In the selected word line 12, the column selection decoder (not shown) selects the specified memory cell or cells 11 by column address signals.
A control circuit (not shown) controls the memory cell 11 selected by the above process for writing or reading data to or from the cell 11.
As shown in FIG. 2, the row selection decoder 20 comprises a decoder 22 such as a NOR logic circuit, buffers 23 and 24 such as NOT circuits.
However, when the conventional semiconductor memory device has a large-scale memory capacity, the memory cells 11 connected by one word line 12 increase, so that the capacitance C of the capacitor 25 shown in FIG. 2 increases in order to drive the decoder 22 and buffers 23 and 24. Accordingly, it is necessary that transistors of the buffers 23 and 24 be large, or of the bipolar type having a higher driving ability.
When the transistors of buffers 23 and 24 are large-sized, the area of memory cells and decoder has to be small even though the wiring patterns are miniaturized.
Furthermore, use of the bipolar transistors requires a larger area than metal oxide semiconductor (MOS) type transistors even though the patterns are small-sized, so that it is difficult for the memory device to be large.